This article looks in detail at how pass-through logic degrades a signal and how this signal degradation can be remedied.
If you’ve read the previous articles, you’re familiar with the fact that implementing pass-through logic with an NMOS switch results in problematic signal degradation. We can greatly improve the signal integrity by using a CMOS transmission gate instead of a NMOS switch. However, it is difficult to motivate yourself to fill a circuit with transmit gates because by doing this we often miss out on the only major benefit that PTL offers, namely a significant reduction in transistor count. A CMOS transmission gate requires not only an additional transistor in the switch itself but also an inverter for the supplemented control signal.
The NMOS switch
Unfortunately, an NMOS transistor is simply not a good device for logic level switching applications. The problem here is that the existence of a current path depends on the presence of a gate voltage that is higher than the source voltage.
This problem is easily solved if the circuit has access to a control voltage that is higher than the voltage levels that will pass through the switch. But in the context of a standard digital circuit, we can never expect to have more than two voltages: the logic-high voltage and the logic-low voltage. So if a 3.3V signal is applied to the gate, the FET simply cannot effectively pass a 3.3V signal from input to output.
An NMOS switch passes a “strong” and a “weak” zero: when a high logic voltage is applied to the gate (to turn the switch on) and a low logic signal is applied to the input terminal, the gate voltage is significantly greater than the voltage at the other two terminals. This results in a low resistance channel between the input and the output. However, the situation is very different when we apply a logic high signal to the input terminal. We no longer have a large voltage difference between the gate and the other two terminals, and electrical performance deteriorates as channel resistance increases.
We can use the following LTspice circuit to experiment with the behavior of an NMOS switch.
A 3.3 V control signal is applied to the gate, and the input signal transits between ground and 3.3 V. The small amount of load capacity represents the input capacity of the downstream circuits.
You can see that the slope of the output signal drops considerably when the difference between the gate voltage and the output voltage drops below a certain level. The output voltage begins to rise very slowly and does not reach the logic high voltage before the start of the next cycle. There is also a significant delay in the negative transition, although the output voltage eventually reaches ground. This graph gives you a good idea of what we mean by zero “strong” and one “weak”.
Can we use an inverter?
You might be thinking that there is a very simple solution to this signal degradation problem: What happens if we apply the PTL signal to the gate of a standard inverter? At first glance, it appears this would reset logic levels, clean the edges, and provide low resistance paths to the supply rail and ground. What could be better?
My guess is that you could get away with it in many situations, but generally it’s not the recommended solution. The problem is that the logic high voltage coming out of the NMOS switch can be low enough to create a conductive channel in the inverter’s PMOS device.
Typically, when the input to an inverter is logic high, the NMOS transistor is fully conductive and the PMOS transistor is completely cut off. But as the input voltage drops below the supply voltage, the voltage from the source to the gate of the PMOS increases, perhaps to the point where non-trivial amounts of current will flow from the source to the drain.
This is a problem, because with the fully conductive NMOS we now have a current path from the supply rail to the ground. The bottom line here is wasted power: the inverter dissipates power not only during switching, but also when the input is logic high.
A basic inverter, then, is not a suitable method of restoring the PTL signal. However, it is almost a suitable method; all we have to do is add a strategically connected PMOS transistor.
The PTL signal restorer
The following LTspice schematic shows an intelligent circuit that can be used to greatly improve the characteristics of the output signal delivered by an NMOS switch.
The operation of the circuit is quite simple. When the input is logic low, the NMOS passes a hard logic low to the inverter. Under these conditions, M2 does not affect the circuit, as its gate voltage is the strong and high logic generated by the inverter.
When the input is logic high, the NMOS initially delivers a low logic high to the inverter. However, this high weak logic is not problematic because it quickly turns into a high strong logic: as soon as the inverter output goes to logic low, M2 turns on, establishing a low resistance path between the output node PTL and the lane fountain.
The following graph demonstrates the efficiency of this circuit.
As you can see, the logic levels have been restored and the lags have been removed. And as a bonus, the signal restoration circuit also produces a high-quality inverted version of the output signal:
This inverted signal can be useful if the downstream circuits use a CMOS transmit gate.
Hope you enjoyed this series on step transistor logic. It’s an interesting alternative to the standard inverter-based digital design, and this article provides you with a means of mitigating the effects of PTL’s lower electrical performance. If you have any arguments against or in favor of transistor-based implementations of digital functionality, feel free to share your thoughts in a comment.