This week, Microsemi announced its latest Unified Design Set to help streamline the FPGA development process.
FPGAs are becoming an increasingly critical component in modern electronics due to their reprogramming and flexibility. But, for many engineers, they remain a complex and daunting form of hardware to design. Microsemi intends to address these difficulties with the launch of a new design suite for its FPGA solutions.
The SmartFusion2 Advanced Development Kit uses a SoC FPGA courtesy of Microsemi.
Let’s take a look at how FPGAs have risen to prominence and why the new Microsemi design suite is important to designers.
FPGAs: increasing complexity and the need for customization
Before the era of FPGAs and CPLDs, designers used tail logic and ASICs (Application Specific Integrated Circuits) to perform specific design tasks. While tail logic easily allowed the creation of custom logic circuits, ASICs provided a method for engineers to combine all of their tail logic into a single IC package. While this was useful for miniaturization, it was not practical for low-volume products as ASICs are essentially custom silicon devices at the metal interconnect level. Designing them is a very expensive process.
One option for creating custom logic tables is with the use of a parallel EEPROM whose address inputs can be used as logic inputs and the 8-bit data output bus as 8 possible logic outputs. However, this method has a few issues, including the inability to implement border-sensitive input and comments.
These problems led the industry to create PLA (Programmable Logic Arrays) and CPLD (Complex Programmable Logic Devices). PLAs and CPLDs allow a designer to create custom logic circuits using a single IC and often integrate comments and flip-flops. While these devices (like Xilinx’s XC9536) have a limited number of logical drives and are not always a replacement for ASICs, they have proven invaluable to the industry.
However, as time progressed and technology improved, CPLDs were quickly replaced by FPGAs, and the number of features built into these devices skyrocketed. FPGAs can now include many features including processors, memory, I / O peripherals, protocol drivers, security, and even up to 500K of logic elements.
While CPLDs can be easily designed using schematic designs, FPGAs are often encoded in languages like VHDL. With so many features, fully utilizing the capacity of an FPGA can be a daunting task requiring multiple software packages.
This week Microsemi announced a new design suite specifically to help designers navigate the often complex waters of developing with a SoC FPGA.
Libero SoC Design Suite V12.0
Microsemi (a subsidiary of Microchip) supplies a wide range of FPGA devices, including PolarFire, IGLOO2, SmartFusion2, IGLOO, and ProASIC3. This week, they announced the release of Libero SoC Design Suite V12.0.
The design suite offers a 60% reduction in run time for time, 25% for location and route, and an 18% reduction in power determination times while providing an average increase of 4 % in quality for large designs (but 10% increases if a PolarFire MPF300 / TS-1 is being used).
While the improvement in placement and routing time has been reduced, what makes the software package more meaningful is that all of these latest Microsemi FPGA families are now unified in one design package. Libero SoC V12.0 has also been designed to simplify migration to and from different FPGA platforms.
Libero SoC Design Flow. Image courtesy of Microsemi.
According to Rajeev Jayaraman, vice president of software for Microsemi’s FPGA business unit, the company wanted to make the design process easier for engineers and also make it easier for them to adopt Microsemi hardware in their designs in the future: “This latest version [of the Libero SoC v12.0] is focused on delivering the many essential elements required for efficient design implementation, while enabling the growing adoption of the low-power PolarFire family in each of our key market segments. “
Libero SoC features include
- Intuitive design flow.
- GUI wizards that guide you through the design process
- One-click flow from synthesis to programming
- Integration of industry standard third party tools
- Rich DirectCores and CompanionCores IP Library
- Availability of reference designs and development kits.
Entrance design using System Builder. Image courtesy of Microsemi.
Libero SoC V12.0 also includes FPGA hardware breakpoints for RTG4 and PolarFire devices, PCIe debugging capabilities, continuous eye monitoring via SmartDebug, improved DDR memory performance (reportedly up to 29% performance Enhanced) and an Enhanced Tools Command Language (TCL). Customers can run a complete design flow on a command line.
Anyone involved in product design knows the importance of getting a product to market as quickly as possible. Product designers also understand and appreciate that FPGAs, while incredibly powerful devices, are complex and require careful planning and management. Any software package that unifies multiple platforms into one while improving processing times is something that will be welcome in any engineering department.