Learn about the effect of parasitic capacitance on the input and how to compensate for it in analog circuit design.
Most internally compensated op-amps are designed for stable operation at any frequency-independent closed-loop gain, including unity gain.
In practice, the presence of capacitances, whether intentional or parasitic, tend to destabilize the circuit and may require additional compensation measures by the user to restore an acceptable phase margin.
Examples of intentional capacitance at the output are found in the sample and hold circuits, spike detectors, and voltage reference boosters with capacitive output shunt. (For capacitive load compensation, see my article on handling large capacitive loads with an operational amplification circuit.)
This article will discuss the effect of parasitic (or parasitic) capabilities on the input, especially on the inverting input.
Types of input capacitance
All op amps exhibit a differential mode input capacitance dodm and a common mode (with inputs attached) input capacitance docm. These are the capacitances exhibited by the input stage transistors, and also by the input protection diodes, if present. (Even though dodm Y docm are internal to the op amp, we display them externally for better viewing.)
In a physical circuit, additional capacitances come into play externally, such as parasitic capacitances of resistors, their leads, and traces of the printed circuit.
In the amplifier example in the figure. 1 B, all the parasites associated with investment inflow have been grouped into a only equivalent capacity donorte.
Figure 1. (a) The parasitic input capabilities of an operational amplifier. (b) Group all the parasites associated with the inverting input as a single capacitance Cn.
We are going to investigate the effect of donorte on the stability of the circuit through the rate of closure (ROC). For this purpose, we set the input source to zero, we break the loop as in Figure 2nd (bottom), apply a test voltage Vt, and calculate the feedback factor H.H(jf) as
Figure 2. (a) Find the feedback factor ß (jf). (b) Speed of closure (ROC) close to 40 dB / dec.
Substituting in equation (1) we obtain, after some algebraic manipulation,
If we focus on the physical meaning of equation (4), we see that donorte and resistance R1||R2 presented to her by the surrounding circuits establish a pole frequency within the feedback loop. Consequently, a signal traveling around the loop will have to deal with two poles, one due to the op-amp and the other due to donorte, with the risk of a phase shift approaching 180 ° and therefore jeopardizing the stability of the circuit.
We can better visualize this in the figure. 2b, showing the graphs of the open-loop gain | to | and the reciprocal of the feedback factor | 1 /H.H(jf) |, where
The pole frequency fpag of H.H(jf) is a zero frequency of 1 /H.H(jf), indicating that the | 1 /H.H(jf) | the curve begins to rise in Fpag. Yes Fpag is low enough compared to the crossover frequency FX, the closing rate will approach 40 dB / dec, indicating a phase margin close to zero.
How to mitigate phase delay due to a single equivalent capacitance
A common cure to combat phase lag because donorte is to introduce leading phase By means of a feedback capacitance. doF through R2, as shown in Figure 3.
figure 3. Exploiting the phase lead introduced by CF to combat the lag due to North.
Equation (1) still holds, as long as we replace R2 with Z2(jf) = R2|| (1 / j2πƒCF). This gives, after some algebraic manipulation,
What is important to note here is that the presence of feedback capacitance creates a zero frequency Fz for H.H(jf), while also lowering the existing pole frequency Fpag somehow (remember that a pole / zero for H.H becomes a zero / pole for 1 /H.H).
How to Select Feedback Capability
There are two common approaches to selecting doF :
Fz = Fpag
Impose Fz = Fpag so that zero cancels the pole in equation (6), giving 1 /H.H = 1 + R2 /R1 throughout, as shown in the figure 4th.
Figure 4. Imposing Fz = FP for a phase margin φ meter ≈ 90 °, or (b) Fz = fX for φ meter ≈ 45 °.
Equating Fz Y Fpag from equation (7) gives, after simplification,
This choice of doF results in a phase margin of around 90 °. To find the crossover frequency. FX we exploit the constancy of the gain bandwidth product in the |a| curve to write (1 + R2 /R1) × FX = Ft, so
Note that the closed-loop gain has two pole frequencies, Fz Y FX, with its –3 dB frequency close to Fz.
Fz = FX
Impose Fz = FX, as the picture shows 4b, for a phase margin of about 45 °. The closed loop gain will now have a higher –3 dB frequency, but at the price of some. in peak hours Y buzz.
To find the required doF, we must first find FX. Taking into account that the high frequency asymptote of 1 /H.H is 1 + donorte /doF, we exploit once again the constancy of the gain bandwidth product in the |a| curve to write (1 + donorte /doF) × FX = Ft, so FX = Ft / (1 + donorte /doF).
Imposing Fz = FX means to impose 1 / (2πR2doF) = Ft / (1 + donorte /doF). Anticipating donorte /doF >> 1, we approximate 1 / (2πR2doF) ≈ Ft / (donorte /doF) = FtdoF /donorte, what do we solve for doF Get
Note that the closed-loop gain now has two matching pole frequencies in FX.
Verification via PSpice
We wish to verify the above considerations by means of the circuit of Figure 5, which uses a constant-gain bandwidth op-amp with Ft = 10 MHz.
Figure 5. An example of an inverting amplifier with a gain of –2 V / V.
Now let’s take a look at Figure 6:
Figure 6. PSpice circuit to trace | to | and | 1 / ß |. (b) The | 1 / ß | Curves for different CF values
With reference to Figure 6, we make the following considerations:
φmeter = 180 ° + ph
The[una(jfX)]- ph[1/[1/ß(jfX)]≈ 180 – 90 –79.2 = 10.8 °
Indicating a circuit on the verge of oscillation.
- For a phase margin of φmeter ≈ 90 °, we use equation (8) to obtain doF = 10 pF. By equation (9) we have FX ≈ 3.33 MHz. As shown in Figure 6b, Now we have
φmeter ≈ 90 °.
- For φ meter ≈ 45 ° we use equation (10) to obtain doF = 1,262 pF. Using the PSpice cursor, we now measure FX = 762.1 kHz and φmeter = 58.8 °. This is better than the anticipated 45 °. To see why, use equation (7) to calculate Fpag = 112.28 kHz and Fz = 630.57 kHz, and then use equation (6) to calculate
Then proceed according to equation (11) to find φmeter = 180 ° – 90 –31.2 = 58.8 °.
Closed-loop AC responses
Figure 7 shows the closed-loop AC responses for the three cases under consideration.
Figure 7. Using PSpice to plot closed-loop AC responses for different CF values.
As expected, the uncompensated response shows a bit of spikes. The peak is almost imperceptible to doF = 1,262 pF, in which case the response shows a matching pole frequency pair at approximately 762 kHz. The answer to doF = 10 pF is the slowest, this being the price we pay for a large phase margin.
As mentioned, this answer contains two pole frequencies, namely, Fz Y FX.
Step responses are shown in Figure 8, which, after discussion of the CA responses, should be self-explanatory.
Figure 8. Using PSpice to plot closed loop step responses for different values of Cf.
Are lost capacitances always a bad thing?
It’s worth noting that parasitic capacitances, while generally undesirable, are not necessarily always a curse.
Suppose that the circuit under consideration had been implemented with R1 = 1.0 kΩ and R2 = 2.0 kΩ, that is, with values diminished for two decades, while still ensuring the same –2 V / V closed-loop gain. Then, according to equation (4), Fpag would do scale up For two decades, at a value far beyond FX So compensation would be unnecessary.
The price for this advantage would of course be a higher power dissipation from the lower resistors. As an exercise, you can find out how low it would be necessary to scale the resistors to achieve a 60 ° phase margin without compensation.