Maria Montero

Input capacitance in analog circuits: how to compensate for the capacitance of …

Learn about the effect of parasitic capacitance on the input and how to compensate for it in analog circuit design.

Most internally compensated op-amps are designed for stable operation at any frequency-independent closed-loop gain, including unity gain.

In practice, the presence of capacitances, whether intentional or parasitic, tend to destabilize the circuit and may require additional compensation measures by the user to restore an acceptable phase margin.

Examples of intentional capacitance at the output are found in the sample and hold circuits, spike detectors, and voltage reference boosters with capacitive output shunt. (For capacitive load compensation, see my article on handling large capacitive loads with an operational amplification circuit.)

This article will discuss the effect of parasitic (or parasitic) capabilities on the input, especially on the inverting input.

Types of input capacitance

All op amps exhibit a differential mode input capacitance dodm and a common mode (with inputs attached) input capacitance docm. These are the capacitances exhibited by the input stage transistors, and also by the input protection diodes, if present. (Even though dodm Y docm are internal to the op amp, we display them externally for better viewing.)

In a physical circuit, additional capacitances come into play externally, such as parasitic capacitances of resistors, their leads, and traces of the printed circuit.

In the amplifier example in the figure. 1 B, all the parasites associated with investment inflow have been grouped into a only equivalent capacity donorte.

(a) (b)
Figure 1. (a) The parasitic input capabilities of an operational amplifier. (b) Group all the parasites associated with the inverting input as a single capacitance Cn.

We are going to investigate the effect of donorte on the stability of the circuit through the rate of closure (ROC). For this purpose, we set the input source to zero, we break the loop as in Figure 2nd (bottom), apply a test voltage Vt, and calculate the feedback factor H.H(jf) as

Equation 1

(a) (b)
Figure 2. (a) Find the feedback factor ß (jf). (b) Speed ​​of closure (ROC) close to 40 dB / dec.

where

Equation 2

Substituting in equation (1) we obtain, after some algebraic manipulation,