This article will examine some properties of the DNL and INL specifications.

In a previous article, we introduced the DNL and INL specifications. Additionally, we examine the relationship between these two linearity metrics. This article will attempt to develop an intuitive understanding of some properties of the DNL and INL specifications.

Before reading any further, we strongly recommend that you quickly review the previous article, What are the DNL and INL specifications of a DAC? Non-linearity in digital to analog converters.

### INL specification review

The ideal transfer function of a three-bit unipolar DAC is shown in Figure 1.

**Figure 1.** Image courtesy of Analog Devices.

**Figure 1.**Image courtesy of Analog Devices.

In a real world implementation, the DAC output voltage levels may deviate from the ideal characteristic above (see the exaggerated example shown in Figure 2).

*Figure 2*

*Figure 2*

The INL for each output level is defined as the deviation of the actual input-output characteristic from the ideal transfer curve. For example, the INL of the output for code 100 is -1.5 LSb in Figure 2 (the ideal output should be 4 LSb but the actual output is 2.5 LSb).

### Implications of an INL less than Â± 0.5 LSb

In this section, we will examine the implications of an input-output characteristic that exhibits an INL less than +0.5 LSb and greater than -0.5 LSb. (Note that many books would say that this DAC has an INL less than Â± 0.5 LSb; from a strict mathematical perspective, this statement is not accurate, but we will use it because it is common and more convenient.) First, let’s examine monotonicity. of this DAC. The output of a monotonic DAC does not decrease for an increase in the input digital code.

The question is: can we have a DAC with an INL less than Â± 0.5 LSb that shows a non-monotonic transfer characteristic? In other words, is it possible to have a decrease in the output for an increase in the digital code while INL is less than Â± 0.5 LSb? If the DAC linearity errors affect two successive output levels in the opposite direction, we may have a decreasing transfer curve.

For example, in Figure 3, the output level for code 011 increases while the output level for 100 decreases. The non-ideal output levels for inputs 011 and 100 are represented by the blue and green dots in the figure.

*figure 3*

*figure 3*

Obviously, a large linearity error can move the green dot under the blue. However, the DAC INL is less than Â± 0.5 LSb. Therefore, in the worst case, we have INL011 = + 0.5 LSb and INL100 = -0.5 LSb. The ideal difference between successive output levels is an LSb. Therefore, we cannot have a decreasing characteristic (the DAC is monotonic) if the INL is less than Â± 0.5 LSb.

#### Calculation of the DNL of this DAC

What about the DNL of a DAC that has an INL less than Â± 0.5 LSb? Can we find an upper limit for the DNL of this DAC?

DNL is the deviation of one output step from the ideal analog value of LSb. The worst case scenario will be the one shown in Figure 4, where the linearity error reduces one output level but increases the next.

*Figure 4*

*Figure 4*

The maximum deviation corresponds to the case where INL.011 = -0.5 LSb and INL100 = + 0.5 LSb. The ideal difference between successive output levels is an LSb. Therefore, the largest possible step in the DAC output will be 2 LSb, giving a DNL of 1 LSb. Therefore, if the INL is less than Â± 0.5 LSb, the DNL is not greater than Â± 1 LSb.

To summarize our discussion so far, if the INL of a DAC is less than Â± 0.5 LSb, the input-output characteristic is monotonic and the DNL is not more than Â± 1 LSb.

It is worth mentioning that monotonicity does not necessarily mean that the INL is less than Â± 0.5 LSb. For example, the input-output characteristic of a Kelvin divider (Figure 5 below) is inherently monotonic. If we increase the input digital code, the output analog voltage will increase or (in the worst case) will keep its value; will not decrease

*Figure 5*

*Figure 5*

Suppose we have a mismatch between the resistors and that the actual values â€‹â€‹are as shown in Figure 6.

*Figure 6*

*Figure 6*

In this case, both the DNL and INL for digital code 001 (when sw1 is on) will be 0.75 LSb. As you can see we have a monotonic DAC, but the INL is greater than 0.5 LSb. Furthermore, this example shows that even with a DNL less than Â± 1 LSb and a monotonic input-output characteristic, there is no guarantee that the INL will be less than Â± 0.5 LSb.

### Interpretation of the shape of a nonlinear transfer characteristic

As mentioned above, the INL of a DAC is a number that provides the maximum deviation of the actual input-output characteristic from the ideal transfer curve. However, this single number cannot provide us with all the information about DAC linearity performance.

For example, we can have two DACs with identical maximum INLs that have completely different frequency domain performance.

The remainder of this article will examine the effect of the INL shape on the frequency content of the DAC output. We do not intend to give a mathematical proof; rather, we will focus on developing an intuitive understanding of the effect of the INL form.

#### An arc-shaped INL

Suppose the input-output characteristic of a non-linear four-bit DAC is as shown by the green line in Figure 7. We will refer to this type of INL performance as an arc-shaped INL.

*Figure 7*

*Figure 7*

We know that a non-linear DAC produces harmonic components. Let’s see what would be the dominant harmonic component of a DAC with an arc-shaped INL. For this purpose, we digitize a sinusoid with four bits and apply a period of this quantized sinusoid to the input-output characteristic of Figure 7. We assume that the frequency of the sinusoid is 1 kHz and that the samples are taken at 10 kHz. . Figure 8 allows us to find the digital code sequence that represents this sinusoid.

*Figure 8*

*Figure 8*

In this figure, the x-axis grid represents the sampling time. The y-axis grid allows us to find the digitized value of each sample. For example, the sample taken at 0.1 ms can be approximated by 1 LSb (which corresponds to the digital code 0001). The sequence of digital code that must be applied to the DAC to produce a period of the sinusoid is 0000, 0001, 0101, 1010, 1110, 1111, 1110, 1010, 0101, 0001.

If the DAC were ideal, it would produce the voltage levels corresponding to the ideal characteristic (the dashed line in Figure 7). The red bars in Figure 9 show these ideal values â€‹â€‹at the sampling times.

*Figure 9*

*Figure 9*

Since the DAC is not ideal, some error will be added to each output level. For the hypothetical nonlinear characteristic in Figure 7, the error voltages correspond to the green bars in Figure 10.

*Figure 10*

*Figure 10*

The actual values â€‹â€‹that the DAC produces are the sum of the value represented by a red bar and the value represented by the corresponding green bar. We know that the red bars represent a 1 kHz sinusoid. What about the green bars? Can we consider them as samples of a sinusoid of a particular frequency? As the cyan curve in Figure 11 shows, the error terms resemble samples of a sinusoid at 2 kHz (the second harmonic of the input sinusoid). So an arc-shaped INL leads to a “dominant” second harmonic at the DAC output.

*Figure 11*

*Figure 11*

#### A symmetrical S-shaped INL

An S-shaped INL for a four-bit DAC is shown in Figure 12.

*Figure 12*

*Figure 12*

Again, we apply the digital code sequence representing a 1 kHz sinusoid (sampled at 10 kHz) to examine the error terms. The error terms are shown as the green bars in Figure 13.

*Figure 13*

*Figure 13*

Note that the error terms look like examples of a function that has half-wave symmetry. A periodic function f

f (tT / 2) = – f

where T denotes the period of the function. For example, the function shown in Figure 14 has half-wave symmetry (we have assumed that it is periodic with a period of T).

*Figure 14*

*Figure 14*

The error terms shown in Figure 13 are actually some samples taken from a similar function to f

When a function has half-wave symmetry, it only has odd-frequency components. This means that the dominant frequency component created by an S-shaped INL is the third harmonic.

To summarize, although the INL conveys information about the linearity of a DAC, this single number cannot provide us with all the information about the linearity performance of the DAC. We can have two DACs with identical maximum INLs that have completely different frequency domain performance. If a DAC has an arc-shaped INL, the second harmonic is dominant; however, with an S-shaped INL, we expect the third harmonic to be dominant.

### Summary

- If the INL of a DAC is less than Â± 0.5 LSb, the input-output characteristic is monotonic and the DNL is not more than Â± 1 LSb.
- With a DNL less than Â± 1 LSb and a monotonic input-output characteristic, there is no guarantee that the INL will be less than Â± 0.5 LSb.
- If a DAC has an arc-shaped INL, the second harmonic is dominant; however, with an S-shaped INL, we expect the third harmonic to be dominant.

To see a complete list of my articles, visit this page.