# DNL and INL specifications of a DAC: Interpretation of the form …

This article will examine some properties of the DNL and INL specifications.

In a previous article, we introduced the DNL and INL specifications. Additionally, we examine the relationship between these two linearity metrics. This article will attempt to develop an intuitive understanding of some properties of the DNL and INL specifications.

Before reading any further, we strongly recommend that you quickly review the previous article, What are the DNL and INL specifications of a DAC? Non-linearity in digital to analog converters.

### INL specification review

The ideal transfer function of a three-bit unipolar DAC is shown in Figure 1.

##### Figure 1. Image courtesy of Analog Devices.

In a real world implementation, the DAC output voltage levels may deviate from the ideal characteristic above (see the exaggerated example shown in Figure 2).

##### Figure 2

The INL for each output level is defined as the deviation of the actual input-output characteristic from the ideal transfer curve. For example, the INL of the output for code 100 is -1.5 LSb in Figure 2 (the ideal output should be 4 LSb but the actual output is 2.5 LSb).

### Implications of an INL less than Â± 0.5 LSb

In this section, we will examine the implications of an input-output characteristic that exhibits an INL less than +0.5 LSb and greater than -0.5 LSb. (Note that many books would say that this DAC has an INL less than Â± 0.5 LSb; from a strict mathematical perspective, this statement is not accurate, but we will use it because it is common and more convenient.) First, let’s examine monotonicity. of this DAC. The output of a monotonic DAC does not decrease for an increase in the input digital code.

The question is: can we have a DAC with an INL less than Â± 0.5 LSb that shows a non-monotonic transfer characteristic? In other words, is it possible to have a decrease in the output for an increase in the digital code while INL is less than Â± 0.5 LSb? If the DAC linearity errors affect two successive output levels in the opposite direction, we may have a decreasing transfer curve.

For example, in Figure 3, the output level for code 011 increases while the output level for 100 decreases. The non-ideal output levels for inputs 011 and 100 are represented by the blue and green dots in the figure.

##### figure 3

Obviously, a large linearity error can move the green dot under the blue. However, the DAC INL is less than Â± 0.5 LSb. Therefore, in the worst case, we have INL011 = + 0.5 LSb and INL100 = -0.5 LSb. The ideal difference between successive output levels is an LSb. Therefore, we cannot have a decreasing characteristic (the DAC is monotonic) if the INL is less than Â± 0.5 LSb.

#### Calculation of the DNL of this DAC

What about the DNL of a DAC that has an INL less than Â± 0.5 LSb? Can we find an upper limit for the DNL of this DAC?

DNL is the deviation of one output step from the ideal analog value of LSb. The worst case scenario will be the one shown in Figure 4, where the linearity error reduces one output level but increases the next.