A CCD is a light-sensitive charge transfer device, and it’s time we took a closer look at exactly how exactly a circuit designer directs the movement of optical information from individual pixel locations to the sensor’s output terminal. As explained above, the fundamental means of performing CCD reading is the application of clock pulses, if you want more context before proceeding, consider learning more about the types of CCD sensors.
Not a typical clock sign
I hesitate to use the term “clock” in this discussion because, in my opinion, a clock signal is almost always a logic-level waveform that interacts with typical digital circuits. CCD voltages are largely of the variety ” non-standard”. High-level clock voltages are often higher than what we use for CMOS logic, and low-level voltages are often spread underground – I picked out some random CCD datasheets to give you some examples of what to expect. Be sure to read the previous article if you don’t understand what I mean by “frame transfer” and “interline transfer”.KAI-1020 from ON Semiconductor: This is an interline transfer device with a resolution of 1000 × 1000 active pixels. Control voltages range from –9 V to +15 V. However, the control signals applied to the chip use 5 V logic; Internal drivers translate the logic signals into the voltage levels required by the load transfer gates.
I thought you might enjoy this fancy 3D rendering of a line-to-line transfer CCD, taken from the KAI-1020 datasheet.
Sony ICX059CL: This is a 752 × 582 pixel interlinear transfer CCD intended for monochrome video cameras. If I understand the datasheet correctly, it uses 15 V to transfer photodiode charge packs to vertical shift registers, –8.5 V to 0 V for vertical transfer clocks, and 0 V to 5 V for horizontal transfer. The following diagram conveys the general architecture of this device.
Diagram taken from ICX059CL data sheet.
Texas Instruments TC281: This 1000 × 1000 pixel image sensor uses frame transfer architecture. Most watches have a low level of –10 V and a high level of +2 V.
The part marked with the × symbol is the light-sensitive pixel array, and the lower half is the storage array. Diagram taken from TC281 datasheet.
Read clock settings
Let’s go back to the semiconductor level and talk about how exactly we persuade charge packets to move from pixel to output terminal. We know this is accomplished by applying sequences of voltages which in turn create sequences of potential wells and potential barriers, but it turns out that there are several different ways to create the necessary variations in potential.
Four Phase Clock The most direct method uses four clock phases. We will consider the four-phase approach in some detail, and then I will briefly mention other schemes. As shown in the diagram below, a four-phase CCD has four gates at each pixel. Therefore, four separate clock signals applied to four different sections of the pixel are needed to move a charge packet to the adjacent pixel.
(Note that if it were a line-to-line transfer CCD, we could say something like “shift register sections” instead of “pixels”, since charge packets do not move through photoactive regions in interline transfer architecture) The process begins in what we will call Stage 1. Clock A and clock B are high, and clock C and clock D are low. (Remember that “high”, which means higher voltage, creates a potential well that draws electrons, and “low” creates a potential barrier that blocks electrons.) Before continuing, take a look at the following diagram and refer to it as we proceed. through the next three stages.
In Level 1, the charge builds up in the potential well below Gates A and B, and cannot move because it is blocked by the barrier below Gates C and D. In Stage 2, Clock A goes down and Clock C goes up. Clocks B and D do not change. This moves all the electrons one step to the right, because now there is a well below gates B and C and a barrier under gates A and D. In Stage 3, Clock B goes down and Clock D goes up. We have pushed the electrons one step to the right again, because now the potential well is under gates C and D. In Stage 4, Clock A goes up and Clock C goes down. We now have a potential well that extends from gate D of one pixel to gate A of the next pixel.Stage 5 it is the same as Stage 1. The charge is completely transferred to the adjacent pixel and the cycle continues.
Three, Two and One Phase Clock The problem with the four phase scheme is that the resolution of the sensor is restricted by the need to have four gates at each pixel. We can decrease the size of the pixels and thus increase the pixel density by reducing the number of clocks required for charge transfer, but to reduce the number of clocks, the applied voltages must be made more complex. Four-phase control are triphasic, pseudo-biphasic, true-biphasic, and virtual phase (ie, single clock) control. Regarding the CCD sensors mentioned above as examples, the KAI-1020 uses a two-phase clock, the ICX059CL uses a four-phase clock, and the TC281 uses a scheme that TI describes as a “proprietary advanced virtual phase” clock.
Now that we’ve discussed the control voltages and charge transfer clock settings, we are ready to explore the analog output signal generated by a CCD image sensor. This will be the subject of the next article.