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Implementing multiplexers with pass-transistor logic

This article describes the efficient multiplexers that can be created using MOSFET in a pass transistor configuration.

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If you've read the previous articles on Step Transistor Logic (PTL), you know this approach to digital design is good and bad. In general, the bad outweighs the good, as evidenced by the preponderance of inverter-based logic in digital integrated circuits of all kinds.

However, we have seen that the pass-through transistor logic can really provide a significant reduction in transistor count, and when it comes to multiplexers, PTL really shines.

The standard CMOS multiplexer

In a way, it is not surprising that PTL leads to efficient multiplexers. Multiplexing is different from basic boolean functions. When we deal with AND, OR, NOT, etc., we are using a logical gate to implement a logical function. That makes sense.

On the other hand, multiplexing is more like a toggle function that we could implement using logic gates because they are immediately available and do the job. In fact, they do the job, but not very efficiently: the door setup shown below seems quite awkward for a task as simple as selecting one of the two input signals, especially considering that each AND gate and OR gate of each inverter require six transistors

A standard 2 to 1 CMOS multiplexer. When S is low logic, Y equals A; when S is high logic, Y is equal to B.

The transmission gate multiplexer

In stark contrast to the inverter-based CMOS implementation, a 2-to-1 PTL multiplexer only requires six transistors: two for each two transmit gates and two for the inverter that provides the complement of the S signal (select).

Multiplexing is essentially a voltage controlled switching, and this type of functionality is so closely related to the operation of the pass transistor that the above circuit needs little explanation. Input signal A is connected to an active-low transmission gate, and input signal B is connected to an active-high transmission gate. When S is low, Y is equal to A; when S is high, Y is equal to B.

A 4 to 1 PTL multiplexer

Pass-transistor multiplexers can be built using either transmission gates or the "lone NMOS" switch type. In terms of pure logical functionality, these are interchangeable: they both pass or block an input signal depending on the state of a control signal. However, if you have read the previous articles on PTL, you know that the transmission gate provides superior electrical performance.

The 4-to-1 multiplexer discussed in this section uses NMOS switches, mainly because the resulting diagram is simpler. Just remember that the NMOS transistor is more or less a placeholder for any type of pass / block element that is used in the actual circuit. In many cases, the preferred implementation will be a transmission gate, or if you want to experiment with these circuits in the lab, you could even replace the FETs with a MEMS relay or switch.

Here is my version of a 4-to-1 PTL multiplexer.

Since there are four input signals, we need a two-bit select signal. These two bits provide four possible binary numbers, and each number corresponds to one of the input signals. The presence (corresponding to high logic) or the absence (corresponding to low logic) of a reversal bar above the S signals can be used to translate the diagram into a functional description:

  • If S0 = 0 and S1 = 0, Y = A.
  • If S0 = 1 and S1 = 0, Y = B.
  • If S0 = 0 and S1 = 1, Y = C.
  • If S0 = 1 and S1 = 1, Y = D.

Note that this circuit requires an inverter for each S signal.In general, we consider the inverter to be a disadvantage associated with using transmission gates instead of NMOS switches, but in this case even the NMOS implementation needs inverters because the multiplexer aims to pass one of the input signals to the output. In other words, a low logic select signal is used not only to block but also to pass, and a logic high select signal is used not only to pass, but also to block. Therefore, we need investors.

Step-transistor multiplexer design

The general idea with PTL multiplexers is to configure the switches connected in series in such a way that a given combination of S inputs passes one of the input signals to the output node. If there are four inputs, as mentioned above, you need two control signals and two transistors connected in series on each input line. If there are eight inputs, you need three control signals and three transistors on each input line. Etc.


You may be wondering about the possibility of using a combination of PMOS switches and NMOS switches. The 4-to-1 PTL multiplexer needs switches that pass a signal when the control voltage is low logic. I accomplished this using an inverted version of the select signal, but if we used PMOS devices for the "low active" switches, we could eliminate the inverters. A PMOS-plus-NMOS solution would look like this:

This would be a functional circuit, but I am confident that the NMOS version is preferred in real life applications, even though the use of PMOS devices reduces the overall transistor count. The electrons have a higher mobility than the holes and, consequently, the electrical performance of an NMOS transistor (which has electrons as the majority charge carriers) is higher than that of a physically equivalent PMOS transistor (which has holes as carriers of majority load).